Dual gate fd-soi transistor

ABSTRACT

Circuit module designs that incorporate dual gate field effect transistors are implemented with fully depleted silicon-on-insulator (FD-SOI) technology. Lowering the threshold voltages of the transistors can be accomplished through dynamic secondary gate control in which a back-biasing technique is used to operate the dual gate FD-SOI transistors with enhanced switching performance. Consequently, such transistors can operate at very low core voltage supply levels, down to as low as about 0.4 V, which allows the transistors to respond quickly and to switch at higher speeds. Performance improvements are shown in circuit simulations of an inverter, an amplifier, a level shifter, and a voltage detection circuit module.

CROSS-REFERENCE TO RELATED APPLICATION

The present patent application is a continuation-in-part of U.S. patentapplication Ser. No. 14/078,236, filed on Nov. 12, 2013, which is herebyincorporated by reference in its entirety.

BACKGROUND

1. Technical Field

The present disclosure relates to dual gate transistors built onsubstrates having a buried oxide layer and, in particular, to the use ofsuch dual gate transistors in integrated circuits to improve circuitperformance.

2. Description of the Related Art

Integrated circuits typically incorporate N-doped and P-doped metaloxide semiconductor field effect transistor (MOSFET) devices in whichcurrent flows through a semiconducting channel between a source and adrain, in response to a bias voltage applied to a gate. When the appliedvoltage exceeds a characteristic threshold voltage V_(t), the deviceswitches on. Ideally, such a switch: a) passes zero current when it isoff; b) supplies large current flow when it is on; and c) switchesinstantly between the on and off states. Unfortunately, a transistor isnot ideal as constructed in an integrated circuit and tends to leakcurrent even when it is off. Current that leaks through, or out of, thedevice tends to drain the battery that supplies power to the device.

For many years, integrated circuit transistor performance was improvedby shrinking critical dimensions to increase switching speed. However,as dimensions of silicon-based transistors continue to shrink,maintaining control of various electrical characteristics, includingoff-state leakage, becomes increasingly more challenging, whileperformance benefits derived from shrinking the device dimensions havebecome less significant. It is therefore advantageous, in general, toincrease switching speed and to reduce leakage current in the transistorby alternative means, including changes in materials and devicegeometry.

One technology that has been developed to control current leakage is thesilicon-on-insulator (SOI) transistor. Examples of conventional planar(2-D) SOI transistor structures built on substrates having a buriedoxide (BOX) layer are shown in FIGS. 1A and 1B and described below ingreater detail. To provide better control of the current flow in thechannel, dual gate SOI transistors have been developed, such as theexemplary dual gate SOI transistor shown in FIG. 2, described in U.S.Patent Publication No. 2010/0264492. A dual gate transistor is anelectronic switching device in which current flow within thesemiconducting channel of a traditional FET is controlled by two gatesinstead of one, so as to influence the current flow from two opposingsurfaces instead of one.

Extending this idea further, 3-D tri-gate transistors have beendeveloped in which the planar semiconducting channel of a traditionalFET is replaced by a 3-D semiconducting fin that extends outward, normalto the substrate surface. In such a device, the gate, which controlscurrent flow in the fin, wraps around three sides of the fin so as toinfluence the current flow from three surfaces instead of one or two.The improved control achieved with such dual gate and tri-gate designsresults in lower threshold voltages, faster switching performance, andreduced current leakage.

BRIEF SUMMARY

According to principles of the various embodiments as discussed herein,an apparatus and method of making are described that incorporate dualgate field effect transistors implemented with fully depletedsilicon-on-insulator (FD-SOI) technology. The FD-SOI dual gate devicesinclude a BOX layer adjacent to the secondary gate that acts as a gateoxide for the secondary gate. Lowering the V_(t) of the transistors canbe accomplished through dynamic secondary gate control in which aback-biasing technique is used to operate the dual gate FD-SOItransistors with enhanced switching performance. By coupling bothprimary and secondary gates of the dual gate FD-SOI devices together,the threshold voltage of the device is lowered during the transitionfrom the off state to the on state, by enhancing the amount of chargerequired to form an inversion region in the channel of the transistor.Meanwhile, conventional direct current (DC) conditions are maintainedduring steady state operation. Consequently, such transistors canoperate at very low core voltage supply levels, down to as low as 0.4 V,which allows the transistors to respond quickly and to switch at higherspeeds. Such high performance devices run on a much wider range of powersupplies and can operate at higher frequencies. Because no componentsare added, integrated circuits that incorporate the dual gate FD-SOIdevices are more area efficient.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

In the drawings, identical reference numbers identify similar elements.The sizes and relative positions of elements in the drawings are notnecessarily drawn to scale.

FIGS. 1A and 1B are cross sections of existing silicon-on-insulatordevices that illustrate partially depleted and fully depleted channels.

FIG. 2 is a cross section of a typical dual gate SOI transistoraccording to the prior art.

FIGS. 3A and 3B are cross-sectional and schematic diagrams of a dualgate FD-SOI PMOS transistor, as described herein.

FIGS. 4A and 4B are cross-sectional and schematic diagrams of a dualgate FD-SOI NMOS flip-well transistor, respectively, as describedherein.

FIG. 5 is a flow diagram showing steps in a method of making a dual gateFD-SOI device, as described herein.

FIG. 6A is a schematic diagram of a dual gate FD-SOI inverter circuitmodule as described herein.

FIG. 6B is a plot of simulated voltage waveforms associated with thedual gate FD-SOI inverter circuit module shown in FIG. 6A.

FIG. 7A is a schematic diagram of a dual gate FD-SOI amplifier circuitmodule as described herein.

FIG. 7B is a plot of simulated amplifier performance associated with thedual gate FD-SOI amplifier circuit module shown in FIG. 7A.

FIG. 8A is a schematic diagram of a level shifter circuit configuredwith a dual gate transistor circuit module, as described herein.

FIG. 8B is a plot of simulated performance associated with the dual gateFD-SOI level shifter circuit module shown in FIG. 8A.

FIG. 9A is a schematic diagram of a core supply detection circuitconfigured with a dual gate transistor circuit module, as describedherein.

FIG. 9B is a plot of simulated performance associated with the coresupply detection circuit module shown in FIG. 9A.

DETAILED DESCRIPTION

In the following description, certain specific details are set forth inorder to provide a thorough understanding of various disclosedembodiments. However, one skilled in the relevant art will recognizethat embodiments may be practiced without one or more of these specificdetails, or with other methods, components, materials, etc. In otherinstances, well-known structures associated with NMOS and PMOStransistors and associated circuits have not been shown or described indetail to avoid unnecessarily obscuring descriptions of the embodiments.

Unless the context requires otherwise, throughout the specification andclaims which follow, the word “comprise” and variations thereof, suchas, “comprises” and “comprising” are to be construed in an open,inclusive sense, that is as “including, but not limited to.”

Reference throughout the specification to “one embodiment” or “anembodiment” means that a particular feature, structure, orcharacteristic described in connection with the embodiment is includedin at least one embodiment. Thus, the appearance of the phrases “in oneembodiment” or “in an embodiment” in various places throughout thespecification are not necessarily all referring to the same aspect.Furthermore, the particular features, structures, or characteristics maybe combined in any suitable manner in one or more aspects of the presentdisclosure.

Reference throughout the specification to integrated circuits isgenerally intended to include integrated circuit components built onsemiconducting substrates, whether or not the components are coupledtogether into a circuit or able to be interconnected. Throughout thespecification, the term “layer” is used in its broadest sense to includea thin film, a cap, or the like and one layer may be composed ofmultiple sub-layers.

Reference throughout the specification to conventional thin filmdeposition techniques for depositing silicon nitride, silicon dioxide,metals, or similar materials include such processes as chemical vapordeposition (CVD), low-pressure chemical vapor deposition (LPCVD), metalorganic chemical vapor deposition (MOCVD), plasma-enhanced chemicalvapor deposition (PECVD), plasma vapor deposition (PVD), atomic layerdeposition (ALD), molecular beam epitaxy (MBE), electroplating,electro-less plating, and the like. Specific embodiments are describedherein with reference to examples of such processes. However, thepresent disclosure and the reference to certain deposition techniquesshould not be limited to those described. For example, in somecircumstances, a description that references CVD may alternatively bedone using PVD, or a description that specifies electroplating mayalternatively be accomplished using electro-less plating. Furthermore,reference to conventional techniques of thin film formation may includegrowing a film in-situ. For example, in some embodiments, controlledgrowth of an oxide to a desired thickness can be achieved by exposing asilicon surface to oxygen gas or to moisture in a heated chamber.

Reference throughout the specification to conventional photolithographytechniques, known in the art of semiconductor fabrication for patterningvarious thin films, includes a spin-expose-develop process sequencetypically followed by an etch process. Alternatively or additionally,photoresist can also be used to pattern a hard mask (e.g., a siliconnitride hard mask), which, in turn, can be used to pattern an underlyingfilm.

Reference throughout the specification to conventional etchingtechniques known in the art of semiconductor fabrication for selectiveremoval of polysilicon, silicon nitride, silicon dioxide, metals,photoresist, polyimide, or similar materials includes such processes aswet chemical etching, reactive ion (plasma) etching (RIE), washing, wetcleaning, pre-cleaning, spray cleaning, chemical-mechanicalplanarization (CMP) and the like. Specific embodiments are describedherein with reference to examples of such processes. However, thepresent disclosure and the reference to certain deposition techniquesshould not be limited to those described. In some instances, two suchtechniques may be interchangeable. For example, stripping photoresistmay entail immersing a sample in a wet chemical bath or, alternatively,spraying wet chemicals directly onto the sample.

Specific embodiments are described herein with reference to dual gateFD-SOI transistors that have been produced; however, the presentdisclosure and the reference to certain materials, dimensions, and thedetails and ordering of processing steps are exemplary and should not belimited to those shown.

FIGS. 1A and 1B provide general information about SOI transistors,familiar to those skilled in the art of transistor design. Inparticular, FIGS. 1A and 1B illustrate what is meant by the terms“partially depleted” and “fully depleted” transistors. FIG. 1A shows apartially depleted MOS SOI transistor 100 in cross section. Likestandard bulk MOS transistors, the partially depleted SOI transistor 100is a three-terminal device in which a voltage applied to a gate 102causes current to flow from a source 104 to a drain 106 through achannel 108. The gate 102 is separated from the rest of the device by athin capacitive gate oxide layer 110. A bulk silicon substrate 114 maybe doped, for example, with negative ions, to form an NWELL region. Thepartially depleted SOI transistor 100 differs from a bulk MOS transistorin that there exists a buried oxide (BOX) layer 112 between the channel108 and the bulk silicon substrate 114. A depletion region 116, depletedof charge, that forms below the channel 108, between the source anddrain regions 104 and 106, is then bounded below by the BOX layer 112.The depletion region can also be referred to as an inversion region.Normally, the presence of the BOX layer prevents the substrate voltagefrom electrically influencing the channel 108. The extent of thedepletion region then depends on the relative dimensions of the variouslayers, as well as source and drain doping profiles, 117 and 118,respectively, and doping concentrations of the source and drain regions.In the case of the partially-depleted SOI device shown in FIG. 1A, thedepletion region 116 does not fill all of the material between thesource and the drain, wherein an un-depleted portion 119 remains at anundetermined floating electric potential. The presence of theun-depleted portion 119 is generally undesirable because it is not wellcontrolled, and yet the associated floating electric potential canelectrically influence the channel and degrade the transistorperformance.

A fully depleted SOI (FD-SOI) transistor 120 is shown in FIG. 1B incross section. Like the partially depleted SOI transistor 100 shown inFIG. 1A, the FD-SOI transistor 120 also has a BOX layer 112. However,the source and drain regions of the FD-SOI device, 124 and 126respectively, are shallower than the source and drain regions 104 and106 of the FD-SOI device 120. As a result, doping profiles 127 and 128are effectively vertical, and the charge characteristics of the channelcan be set by the doping concentrations such that a fullycharge-depleted region 116 forms between the shallow source and drainregions 124 and 126, bounded below by the BOX layer 112, in response toapplication of a bias voltage to the gate 102. Because all of thematerial between the source and drain is charge-depleted, theun-depleted portion 119 shown in FIG. 1A has been eliminated as apossible cause of transistor degradation.

FIG. 2 shows a generalized example of the architecture of a typical dualgate SOI transistor 130 as shown in U.S. Patent Publication No.2010/0264492. Like the conventional MOS and SOI devices, the dual gateSOI transistor 130 has a primary gate 102, a source 104 and a drain 106on either side of a channel 108, wherein the primary gate 102 isseparated by a thin primary gate oxide layer 110. In addition, the dualgate SOI transistor 130 includes a secondary gate 132, which isseparated from the channel region 108 by a thin, secondary gate oxidelayer 134. Both the primary and secondary gates 102 and 132 can bebiased so as to influence current flow in the channel region 108. Thedual gate SOI transistor 130 is usually operated by coupling thesecondary gate 132 to a supply voltage or to ground, while a biasvoltage is applied to the primary gate 102.

FIGS. 3A and 4A show cross-sectional representations of a dual gate PMOSFD-SOI transistor 136 and a dual gate NMOS FD-SOI transistor 138,respectively, as disclosed herein. The cross-sectional views moreclearly show the structure of the dual gate FD-SOI transistors fordirect comparison with the conventional dual gate transistor 130 shownin FIG. 2. Like the dual gate SOI transistor 130, dual gate FD-SOItransistors are four-terminal devices having a source S, a drain D, aprimary gate G1, and a secondary gate G2. In the dual gate PMOS FD-SOItransistor 136 shown in FIG. 3A, for example, the channel 137 can becontrolled by a bias voltage applied to either the primary gate G1, orthe secondary gate G2, or both.

Unlike the dual gate SOI transistor 130, in the embodiment shown in FIG.3A, the secondary gate G2 is the substrate, which is doped to form theNWELL region 114, as is customary and well known in the art.Furthermore, the secondary gate G2 can be biased by applying a voltageto the NWELL region 114 of the substrate via a front side NWELL contact140. The secondary gate G2 is spaced apart from the channel 137 by asecondary gate oxide layer which, in the embodiment shown, is the BOXlayer 112. Thus, between G1 and G2, there exist two capacitances,C_(gate) across the primary gate oxide layer 110, and C_(box) across theBOX layer 112. The BOX layer 112 provides a much thicker capacitivedielectric than does the gate oxide layer 110.

It is noted that the PMOS FD-SOI device shown in FIG. 3A is formed inthe NWELL region 114, in the conventional way that is well known in theart, whereas the NMOS FD-SOI device shown in FIG. 4A is also formed inan NWELL region 114, which is unconventional. Typically an N-typetransistor is formed in a PWELL region. Depending on the circuitapplication of the FD-SOI device, the polarity of the well doping, aswell as the doping concentration, can be adjusted so as to produce themost desirable electrical effect. Consequences of such design choicescan be evaluated using device simulations.

In the circuit applications disclosed herein, the secondary gates ofeach of the dual gate FD-SOI transistors can be thought of as beingshort-circuited to their respective primary gates. Hence, G1 and G2 areshown as tied together in FIGS. 3A and 4A by electrical connections 142and 144, respectively. The effect of coupling the primary and secondarygates together is that the secondary gate back-biases the transistor tocreate an inversion layer in the channel region faster than usual. Thiscauses the threshold voltage to be lower so that the device turns oneasier, and the transition time from the low state to the high state istherefore shorter. Because the primary gate is also biased high at thesame time, the back-biasing translates to an improvement in theswitching performance.

The back-biasing technique is not effective when used with dual gatebulk transistors because the performance of bulk devices is subject tolimitations that do not affect FD-SOI devices. One such limitation isthat the bias voltage is limited to a range of about 200-300 mV in bulktechnologies, because the gate oxide is so thin. This limitation doesnot exist in an FD-SOI device because the source and drain are fullyisolated from the substrate by the BOX layer 112. Another limitationthat affects bulk transistors is that the effectiveness of a body biasdegrades as transistor dimensions shrink in subsequent technologygenerations. The body bias becomes ineffective at about the 20 nm node.

The dual gate FD-SOI transistors 136 and 138 as described herein arerepresented schematically in FIGS. 3B and 4B, configured as pass gates.It is noted that the gate terminals G1 and G2 are coupled together bythe electrical connectors 142, 144 during operation of both the PMOS andNMOS devices. The output voltage of a pass gate has the same value asits input. Thus, a pass gate can be made by coupling together theprimary and secondary gates of the dual gate FD-SOI transistors 136 and138. It is further noted that the PMOS FD-SOI transistor 136 switches onin response to a negative voltage applied to the gates G1 and G2,because in a PMOS device, charge carriers in the channel 137 arepositively charged holes. Thus, the PMOS device is shown as having aninverted input at the primary gate G1.

FIG. 5 shows high level steps in a method 150 of making the dual gateFD-SOI transistors 136 and 138 shown in FIGS. 3A and 4A, respectively.

At 152, a starting material is provided as a silicon-on-insulator (SOI)wafer that includes the BOX layer 112 over a heavily N-doped region,which is the NWELL region 114. In one embodiment, the BOX layer 112 hasa thickness within the range of about 15-30 nm so that it can sustainapplication of up to about ±3.3 V to the NWELL region 114 withoutexperiencing a structural breakdown. The thickness of the BOX layer 112is large compared with the gate oxide layer 110 separating the primarygate G1 from the channel 137. However, the BOX layer 112 is thincompared with a typical BOX layer, which can be as thick as about 100nm. An SOI wafer of the ultrathin body and buried oxide (UTBB) type, forexample, will provide the desired thickness of the BOX layer. The SOIwafer includes an active region above the BOX layer 112 in which thetransistor is formed. The active region thickness can be in the range ofabout 10-200 nm, but is desirably between 10 and 50 nm for the devicesdescribed herein.

At 153, the gate oxide layer 110 is formed on the surface of the activeregion of silicon by depositing a thin layer of silicon dioxide, or ahigh-k dielectric material such as halfnium oxide, for example. The gateoxide thickness is typically about 10 nm.

At 154, the primary gate 102 is deposited and both the gate 102 and thegate oxide layer 110 are patterned using standard deposition,lithography, and etching techniques well known in the art. The primarygate 102 can be made of polysilicon or metal, common materials wellknown in the art.

At 156, the primary gate 102 is used as a mask for doping the source anddrain regions 104 and 106, respectively, by implanting either positiveions or negative ions, as is known in the art. The penetration depth ofions implanted into the silicon substrate is limited by the location ofthe BOX layer 112.

At 158, the front side NWELL contact 140 is formed by etching andfilling a trench that extends through the BOX layer 112 to the top ofthe NWELL region 114.

At 159, the primary gate G1 (102) is coupled to the secondary gate G2 bythe electrical connection 142. The electrical connection 142 can be anintegral connection made according to a wiring design at an interconnectlayer, for example, metal 1, formed after the transistor is complete.

While the techniques used to form layers within the dual gate FD-SOItransistors 136 and 138 are well known, formation of the structures isunique to the disclosed embodiments. In particular, such structuresinclude the contact 140 to the NWELL region 114 for use as a secondarygate, and separation of the secondary gate from the channel 137 by theBOX layer 112.

FIGS. 6A-9 show exemplary embodiments of different circuit elementsimplemented using the dual gate FD-SOI devices 136 and 138, anddemonstrate their advantages over conventional circuit elements. In eachcircuit application, performance improvements are achieved byback-biasing the devices i.e., biasing the secondary gate G2 byconnecting it to the primary gate G1, and applying a bias voltage toboth gates. Through such a back-biasing technique, current within thechannel 137 is controlled from both the top side and the back side,instead of only from one side. The channel 137 is therefore moreresponsive to the biasing voltage. Furthermore, instead of the BOX layerisolating the substrate 114 from the active region, the substrate 114 isused to control the active region dynamically, through the BOX layer112. The greater degree of sensitivity achieved by the BOX-controlledback-biasing technique means that the device turns on at a lower biasthreshold voltage V_(t), and the current in the channel responds morequickly to voltage changes, which means that the device can operate athigher frequencies.

Such performance enhancements are evident in the plots below, which arederived from circuit simulations. Simulation results were obtained usingELDO circuit simulation software available from Mentor Graphics, Inc. ofWilsonville, Oreg. In the circuit simulations, conventional transistorparameters are replaced by parameters describing the dual gate FD-SOItransistors, which are then driven using the back-biasing technique.

FIG. 6A shows a dual gate inverter 160 created by coupling together thePMOS dual gate FD-SOI device 136 and the NMOS dual gate FD-SOI device138 in a standard inverter configuration. The standard inverterconfiguration includes a supply voltage V_(DD) applied to the sourceterminal of the PMOS device 136, ground applied to the drain terminal ofthe NMOS device 138, an input voltage V_(in) applied to both the primarygates, and the drain terminal of the PMOS device 136 coupled to thesource terminal of the NMOS device 138 at the output of the inverter. Inaddition, in the present dual gate inverter 160, the primary andsecondary gates G1 and G2 of each device are shorted together at 142 and144, respectively.

FIG. 6B shows simulation results testing the performance of the dualgate inverter 160 as shown in FIG. 6A. FIG. 6B includes a top panel 168and a bottom panel 169. The top panel 168 shows a time-varying inputvoltage signal V_(in), which resembles a triangular wave having amaximum amplitude of 2 V and a frequency of 1 GHz. The bottom panel 169shows time-varying output voltage signals V_(out0), which correspond toa conventional inverter circuit element, and V_(out1), which correspondsto the dual gate inverter 160 as described herein. An ideal inverteroutput signal would look like an upside-down V_(in), such that wheneverV_(in) is on at 2.0 V, V_(out) is off at 0 V, and vice versa.

By comparing the bottom panel 169 with the top panel 168, it is clearthat the signal V_(out1) responds faster than does the signal V_(out) tochanges in the input voltage signal V_(in). For example, as soon asV_(in) rises, V_(out1) drops, whereas there is a delay Δt 171 beforeV_(out) responds. Taking into account both the rise time and fall timedelays associated with V_(out), a performance improvement of nearly 30%is evident in the simulation of the dual gate inverter 160. The fasterresponse associated with the dual gate inverter 160 can be attributed tothe channels 137 in each of the NMOS and PMOS devices being influencedsimultaneously from both sides by the primary and secondary gates G1 andG2, wherein G2 is the N-doped substrate acting through the BOX layer112. Under the influence of both G1 and G2, formation of the inversionregion that provides a conduction path from source to drain via thechannel 137 occurs faster.

FIG. 7A shows a dual gate amplifier 170 created by coupling the PMOSdual gate FD-SOI device 136 and a reference resistor R_(ref) in astandard amplifier configuration. The standard amplifier configurationincludes a supply voltage V_(DD) applied to the source terminal of thePMOS device 136 through the reference resistor R_(ref), ground appliedto the drain terminal of the PMOS device 136, and an input voltageV_(in) applied to the primary gate G1. In addition, in the present dualgate amplifier 170, the primary and secondary gates G1 and G2 of thePMOS device 136 are shorted together at 142.

FIG. 7B shows simulation results testing the performance of the dualgate amplifier 170 as shown in FIG. 7A. The expected behavior of anamplifier is to boost the magnitude of the input signal to a highervalue. FIG. 7B shows the magnitude in decibels of the amplifier gain,which is the ratio of V_(out)/V_(in). The bottom gain valueV_(out0)/V_(in)=2.66 dB corresponds to a conventional amplifier circuitelement and the top gain value V_(out1)/V_(in)=7.07 dB corresponds tothe dual gate amplifier 170 as described herein. The dual gate amplifier170 therefore shows a gain that is about 2.7 times larger than theconventional amplifier gain. By coupling the primary and secondary gatesG1 and G2 together, the threshold voltage of the dual gate transistor iseffectively lowered, which boosts the output voltage.

FIG. 8A shows a dual gate level shifter circuit 180 created by couplingtwo conventional PMOS devices and two NMOS dual gate FD-SOI devices 138a and 138 b in the level shifter configuration shown. The level shifterconfiguration includes applying a supply voltage V_(DD) to the sourceterminals of the PMOS devices, and cross-coupling the PMOS devices tothe source terminals of the NMOS dual gate FD-SOI devices 138 a,b. Thelevel shifter configuration further includes coupling the gates of theNMOS dual gate FD-SOI devices 138 a,b across an inverter 182, andgrounding the drain terminals of the NMOS dual gate FD-SOI devices 138a,b. In the present dual gate level shifter circuit 180, the primary andsecondary gates G1 and G2 in each of the NMOS devices 138 a,b areshorted together at 144 a and 144 b, respectively, so that a biasvoltage applied to the primary gate activates the secondary gatesimultaneously, resulting in a faster turn-on time for the transistor.

FIG. 8B shows simulation results testing the performance of the dualgate level shifter circuit 180 as shown in FIG. 8A against that of aconventional level shifter that includes conventional NMOS devices.Expected behavior of the level shifter circuit is to shift the magnitudeof the input signal to a higher value so that a low core supply voltageis sufficient to operate the circuit.

FIG. 8B includes a top panel 188 and a bottom panel 189. The top panel188 shows a time-varying input voltage signal V_(in), which resembles asquare wave having a maximum amplitude of about 0.4 V and a frequency of1 MHz, corresponding to a period of 1.0 μs. An ideal level shifteroutput signal would look similar to V_(in), except the amplitude wouldbe shifted to a higher value. It is observed that the top panel 188shows an output signal V_(out0) that is shifted to a higher voltagelevel of about 1.8 V, but that V_(out0) remains at 1.8 V continuously.

In contrast, the bottom panel 189, which corresponds to the dual gatelevel shifter circuit 180 as described herein, shows that the improvedoutput voltage signal V_(out0) also boosts the 0.4 V input signal up toabout 1.8 V, but the dual gate level shifter circuit 180 is able torespond to the input signal with only about a 0.3 μs delay. At therelatively low frequency of 1 MHz, V_(out1) has the desired square waveshape. The faster response associated with the dual gate level shifter180 can be attributed to the channel 137 in each of the NMOS devicesbeing influenced simultaneously from both sides by primary and secondarygates. Further discussion of level shifter circuit configurations thatuse dual gate transistors is found in U.S. patent application Ser. No.14/078,236.

FIG. 9A shows a core supply detection circuit 190. A core supplydetection circuit is a voltage detection circuit for low voltage levels,for example, a low voltage core supply. At the input stage a dual gateinverter 160 of the type shown and described with respect to FIG. 6Areceives an input voltage V_(in). In some embodiments V_(in) can becoupled to V_(DD) as the input voltage. In other embodiments, V_(in) canbe other voltages. The core supply detection circuit 190 can beconfigured with one or more dual gate inverters 160 at differentlocations beyond the one example shown. Again, the NMOS deviceinterconnect is formed with the primary and secondary gates coupledtogether for improved performance in detecting low voltages, asexplained herein. When both the primary and secondary gates areinfluencing the channel 137 through the BOX layer 112, the thresholdvoltage of the device is effectively lowered, such that the dual gateinverter 160 turns on in response to application of a lower biasvoltage. As a result, the detection circuit 190 is more sensitive to lowvoltages than is a conventional detection circuit.

FIG. 9B shows simulation results testing the performance of the coresupply detection circuit 190 as shown in FIG. 9A against that of aconventional core supply detection circuit that includes conventionalinverters at every stage. Expected behavior of the core supply detectioncircuit is to turn on when V_(IN) switches off, and remain high untilV_(IN) switches on again. FIG. 9B includes a top panel 198 and a bottompanel 199. The top panel 198 shows a time-varying input voltage signalV_(IN), which resembles a square wave having a maximum amplitude ofabout 0.3 V and a frequency of 1 MHz, corresponding to a period of 1.0μs. An ideal core supply detection circuit output signal would looksimilar to V_(IN), except the signal amplitude would be boosted to ahigher value, and inverted with respect to V_(IN). It is observed thatthe top panel 198 shows an output signal V_(COFF) that remains at 1.8 Vcontinuously, indicating failure at a core supply of 0.3 V.

In contrast, the bottom panel 199, which corresponds to the core supplydetection circuit 190 as described herein, shows that the improvedoutput voltage signal V_(COFF2) also boosts the 0.3 V input signal up toabout 1.8 V, but the core supply detection circuit 190 is able torespond to the input signal with substantially no delay. At therelatively low frequency of 1 MHz, V_(COFF2) has the desired invertedsquare wave shape and greater amplitude. The faster response associatedwith the dual gate core supply detection circuit 190 can be attributedto the channel 137 in the dual gate NMOS device within the inverter 160being influenced simultaneously from both sides by primary and secondarygates.

The various embodiments described above can be combined to providefurther embodiments. All of the U.S. patents, U.S. patent applicationpublications, U.S. patent applications, foreign patents, foreign patentapplications and non-patent publications referred to in thisspecification and/or listed in the Application Data Sheet areincorporated herein by reference, in their entirety. Aspects of theembodiments can be modified, if necessary to employ concepts of thevarious patents, applications and publications to provide yet furtherembodiments.

It will be appreciated that, although specific embodiments of thepresent disclosure are described herein for purposes of illustration,various modifications may be made without departing from the spirit andscope of the present disclosure. Accordingly, the present disclosure isnot limited except as by the appended claims.

These and other changes can be made to the embodiments in light of theabove-detailed description. In general, in the following claims, theterms used should not be construed to limit the claims to the specificembodiments disclosed in the specification and the claims, but should beconstrued to include all possible embodiments along with the full scopeof equivalents to which such claims are entitled. Accordingly, theclaims are not limited by the disclosure.

1. A method of forming a silicon-on-insulator dual gate transistorcircuit, the method comprising: electrically coupling together primaryand secondary gates of a silicon-on-insulator dual gate transistor;electrically coupling a source terminal of the silicon-on-insulator dualgate transistor to a first circuit element; and electrically coupling adrain terminal of the silicon-on-insulator dual gate transistor to asecond circuit element.
 2. The method of claim 1 wherein the first andsecond circuit elements include one or more of a power supply, anotherelectronic device, or a connection to ground.
 3. The method of claim 1wherein the dual gate transistor includes a buried oxide layer adjacentto the secondary gate.
 4. The method of claim 1 wherein the dual gatetransistor is an NMOS dual gate transistor, the primary and secondarygates are both coupled to a core power supply, the drain terminal isgrounded, and the source terminal is coupled to a PMOS transistor. 5.The method of claim 1 wherein the dual gate transistor is an NMOS dualgate transistor, the primary and secondary gates are both coupled to aninput, the drain terminal is grounded, and the source terminal iscoupled to a PMOS transistor.
 6. The method of claim 1 wherein the dualgate transistor is a PMOS dual gate transistor, the primary andsecondary gates are both coupled to an input, the source terminal iscoupled to a power supply, and the drain terminal is coupled to an NMOStransistor.
 7. The method of claim 1 wherein the dual gate transistor isan NMOS dual gate transistor, the primary and secondary gates are bothcoupled to an input, the drain terminal is grounded, and the sourceterminal is coupled to an output load.
 8. The method of claim 1 whereinthe dual gate transistor is an NMOS dual gate transistor, the primaryand secondary gates are both coupled to an input of an inverter, thedrain terminal is grounded, and the source terminal is coupled to apower supply through a PMOS transistor.
 9. The method of claim 1 whereinthe dual gate transistor is an NMOS dual gate transistor, the primaryand secondary gates are both coupled to an output of an inverter, thedrain terminal is grounded, and the source terminal is coupled to apower supply through a PMOS transistor.
 10. The method of claim 1wherein the dual gate transistor is a first PMOS dual gate transistor,the primary and secondary gates are both coupled to a second PMOS dualgate transistor, the drain terminal is coupled to an NMOS dual gatetransistor, and the source terminal is coupled to a power supply.
 11. Acircuit module, comprising: a silicon-on-insulator dual gate transistor;a first circuit element coupled to a source terminal of thesilicon-on-insulator dual gate transistor; a second circuit elementcoupled to a drain terminal of the silicon-on-insulator dual gatetransistor; and an electrical conductor extending from the primary gateto the secondary gate that electrically couples the primary andsecondary gates to one another.
 12. The circuit module of claim 11wherein the dual gate transistor includes a buried oxide layer adjacentto the secondary gate.
 13. The circuit module of claim 11 wherein thefirst circuit element is a PMOS transistor, the second circuit elementis a ground connection, and the dual gate transistor is an NMOS dualgate transistor configured with the primary and secondary gates coupledto a core supply.
 14. The circuit module of claim 11 wherein the firstcircuit element is a power supply coupled to the source through aresistor, the second circuit element is a ground connection, and thedual gate transistor is an NMOS dual gate transistor configured withprimary and secondary gates coupled to an input terminal of theamplifier circuit module.
 15. The circuit module of claim 11 wherein thedual gate transistor is part of a level shifter circuit in which thefirst circuit element is power supply coupled to the source through aPMOS transistor, the second circuit element is a ground connection, andthe dual gate transistor is an NMOS dual gate transistor configured withprimary and secondary gates coupled to an input terminal of an inverter.16. The circuit module of claim 11 wherein the dual gate transistor ispart of a level shifter circuit in which the first circuit element ispower supply coupled to the source through a PMOS transistor, the secondcircuit element is a ground connection, and the dual gate transistor isan NMOS dual gate transistor configured with primary and secondary gatescoupled to an output terminal of an inverter.
 17. An inverter circuitmodule, comprising: a PMOS dual gate transistor having primary andsecondary gates coupled to an input terminal and a source terminalcoupled to a power supply; and an NMOS dual gate transistor havingprimary and secondary gates coupled to the input terminal, and a drainterminal coupled to ground, an output terminal of the inverter coupledto both a drain terminal of the PMOS dual gate transistor and a sourceterminal of the NMOS dual gate transistor.
 18. A pass gate comprising anNMOS dual gate transistor configured with primary and secondary gatescoupled together.
 19. A pass gate comprising a PMOS dual gate transistorconfigured with primary and secondary gates coupled together.
 20. Amethod of making a silicon-on-insulator dual gate transistor, the methodcomprising: providing a silicon-on-insulator substrate including aburied oxide layer over an N-doped region; forming a primary gate thatincludes a gate electrode and a gate oxide; implanting source and drainregions with dopant ions using the primary gate as a mask; forming afront side contact to the N-doped region for use of the N-doped regionas a secondary gate; and coupling the primary gate to the secondarygate.